In a series of components such as BOC components or else in CSP (Chip Size Package) components, FBGA (Fine Pitch Ball Grid Array), TBGA (Tape Ball Grid Array) or μBGA components or the like, the chips are mounted on substrates whose dimensions approximately correspond to those of the chips to be mounted. The various designations are in part manufacturer-typical indications and identify differences or subtleties in the structural design. In the interests of a structural height that is as small as possible, in some components the chip rear sides are not covered, rather at most merely the particularly sensitive chip edges are enclosed by a molding compound. This last is effected by dispensing a suitable molding compound (potting compound) around the chip edges. If the chip rear side is also to be concomitantly protected in addition, it is necessary to use complicated printing or casting methods. It goes without saying that the different materials used for the substrate, the chip and the potting compound have in some instances considerably different mechanical properties and, in particular, different thermal expansion coefficients. For the substrate, use is made of the customary printed circuit board materials, such as hard paper or glass fiber materials, in which synthetic resin is usually used as a binder.
Examples of such semiconductor components are found in U.S. Pat. No. 5,391,916 A, which describes a semiconductor component provided with a potting compound, or in U.S. Pat. No. 5,293,067 A, which describes a special chip carrier for a chip on board (COB) component in order to reduce the mechanical stress.
Through suitable material selection, the expansion coefficients can be co-ordinated with one another in a certain way such that the difference in the expansion coefficients between the respective material pairing becomes as small as possible.
However, there is virtually no possibility of complete matching. This has the fatal consequence, particularly in the case of BOC or COB components, that the latter, if they are protected with an additional molding covering, are subjected to an extreme stress during normal use. This stress is essentially based on the “bimetal effect”, which results when different materials having different expansion coefficients are joined together in layers.
In order at least to reduce the stress between the substrate and the chip, the mounting thereof on the substrate is usually effected with the interposition of a tape that compensates for thermal stresses. In any event, there are then still significant differences in the respective expansion coefficients between the material pairings of Si chip/molding compound and molding compound/substrate that are directly in contact with one another. In the worst-case situation, this may result in a separation of the connection and thus possibly the total failure of the component.
As already mentioned in the introduction, various complicated methods have hitherto been carried out for protecting the chips. Thus, by way of example, dispensing, in order to protect the particularly sensitive chip edges, or printing or molding, in order to achieve a complete protection of the chip including the rear side thereof. However, it has not been possible to eliminate, or eliminate sufficiently, the effects of the thermomechanical stresses between the material pairings, so that stress-dictated component failures always have to be reckoned with. However, solution approaches such as material and design changes and a tape underlay have caused other problems, such as uncovered fuses.